Resistive Random Access Memory Rram

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Resistive Random Access Memory Rram

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Author : Shimeng Yu
language : en
Publisher: Morgan & Claypool Publishers
Release Date : 2016-03-18

Resistive Random Access Memory Rram written by Shimeng Yu and has been published by Morgan & Claypool Publishers this book supported file pdf, txt, epub, kindle and other format this book has been release on 2016-03-18 with Technology & Engineering categories.

RRAM technology has made significant progress in the past decade as a competitive candidate for the next generation non-volatile memory (NVM). This lecture is a comprehensive tutorial of metal oxide-based RRAM technology from device fabrication to array architecture design. State-of-the-art RRAM device performances, characterization, and modeling techniques are summarized, and the design considerations of the RRAM integration to large-scale array with peripheral circuits are discussed. Chapter 2 introduces the RRAM device fabrication techniques and methods to eliminate the forming process, and will show its scalability down to sub-10 nm regime. Then the device performances such as programming speed, variability control, and multi-level operation are presented, and finally the reliability issues such as cycling endurance and data retention are discussed. Chapter 3 discusses the RRAM physical mechanism, and the materials characterization techniques to observe the conductive filaments and the electrical characterization techniques to study the electronic conduction processes. It also presents the numerical device modeling techniques for simulating the evolution of the conductive filaments as well as the compact device modeling techniques for circuit-level design. Chapter 4 discusses the two common RRAM array architectures for large-scale integration: one-transistor-one-resistor (1T1R) and cross-point architecture with selector. The write/read schemes are presented and the peripheral circuitry design considerations are discussed. Finally, a 3D integration approach is introduced for building ultra-high density RRAM array. Chapter 5 is a brief summary and will give an outlook for RRAM’s potential novel applications beyond the NVM applications.

Resistive Random Access Memory

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Author : Arnab Hazra
language : de
Publisher: LAP Lambert Academic Publishing
Release Date : 2012-04

Resistive Random Access Memory written by Arnab Hazra and has been published by LAP Lambert Academic Publishing this book supported file pdf, txt, epub, kindle and other format this book has been release on 2012-04 with categories.

Resistive Random Access Memory (RRAM) is a transistor free non-volatile dynamic RAM cell with very simple Metal-Insulator-Metal (MIM) structure and very high switching speed and high density memories. Different types of oxides like Transition Metal Oxides, Perovskite Oxides etc are used as the insulating dielectric layer of the capacitor like MIM structure. This ion-conducting oxide insulating layer can change its resistance by externally stimulated electric pulses with different amplitude and frequency. The steps precondition the system which can subsequently be switched between high conductive ON or Low Resistive State (LRS) and a less conductive OFF or High Resistive State (HRS). In this experimental study Sol-gel derived Titanium Dioxide (TiO2) is considered as the ion conducting insulating dielectric material of this RRAM device. Pd (Ag)/TiO2 /Pd (Ag) Metal-Insulator-Metal structure for RRAM devices have been designed and fabricated and studied in this book. Different analytical models and explanations to establish the mechanism behind the Transition metal oxide based RRAM device and Resistive Switching phenomenon are the addition features of this book.

Resistive Switching Random Access Memory Rram Scaling Materials And New Application

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Author : Yi Wu
language : en
Publisher:
Release Date : 2013

Resistive Switching Random Access Memory Rram Scaling Materials And New Application written by Yi Wu and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013 with categories.

The demand for solid-state memories has been increasing rapidly in recent years thanks to the increasing demand from portable electronic devices like smartphones and tablets. Semiconductor non-volatile memories (NVMs), such as NAND and NOR Flash, is the fastest-growing segment in today's solid-state memories. Looking forward, the further scaling of flash memory devices is becoming more challenging: (1) the high electric fields required for the programming and erase operations; (2) the stringent leakage requirements for long term charge storage. While innovations in cell structure and device materials may help extend Flash memory for another couple of technology nodes, alternative memory solutions must be explored for future non-volatile memory applications. There are varieties of emerging memory technologies being researched as possible candidates for next-generation NVM, such as Phase Change Memory (PCM), Spin Torque Transfer Magnetic Random Access Memory (STT-MRAM), and Resistance Switching Random Access Memory (RRAM), etc. Among these candidates, metal oxide RRAM has attracted plenty of attention in the past a few years. It is one of the most promising candidates for future NVM application for its superior scalability, fast speed, low programming current, long endurance, excellent read immunity, and good retention properties. However, in order to meet the practical application requirements, the RRAMs demonstrated to date still need improvements in the following areas: (1) further scaling down the device size; (2) minimize the switching parameters variations; (3) eliminating the forming process. This thesis aims at addressing and elucidating the above challenges and exploring possible solutions through innovations in device materials and structures, new fabrication techniques, and understanding the device physics through comprehensive device characterizations. While RRAM has the potential as a non-volatile memory technology, another emerging application is the use of RRAM as electronic synapse element for hardware implementation of neuromorphic computing. Due to RRAM's multilevel storage capability and low power consumption, it can behave like an analog memory emulating the function of plastic synapses in a neural network. In this thesis, RRAM devices have been investigated as electronic synapses for demonstrating learning rule. To explore the scaling limit of RRAM cells, carbon nanotube (CNT), which is a naturally single-digit-nm material, is utilized as the memory electrode. We report the first AlOx-based resistive switching memory (RRAM) using carbon nanotubes (CNT) as contact electrodes. CNTs with average diameter of 1.2nm effectively localize the conduction filaments (CFs). The Al/AlOx/CNT device successfully switches over 1E4 cycles with less than 5 [microamperes] programming current. Extreme scaling of the device down to 6nm × 6nm is realized by the CNT/AlOx/CNT cross-point structure and 1E4 switching cycles are achieved. Although CNTs have unique properties such as mechanical stiffness, strength, and high thermal and electrical conductivity compared to other materials, it is very challenging to implement CNTs in mass production for its fabrication difficulties and high production cost. A simple process with electron beam lithography (EBL) was used to fabricate devices with active areas from tens of æm to nm along with atomic-layer deposition (ALD). Scaling trends for forming and switching characteristics are presented. For the smallest device with an active area of a few nm in diameter, AC switching endurance of 1E8 cycles with an over 100× resistance window is demonstrated. In addition, multiple resistance states are shown to be stable after 1E5 read cycles and 1E5 seconds baking at 150 °C. Because EBL is limited by its low throughput and not adequate for large-scale memory manufacturing, low-cost and high-throughput block-copolymer self-assembly lithography serves as a promising extension of optical lithography for technology nodes beyond 10 nm. The fabricated bi-layer TiOx/HfOx devices show excellent performance: low forming voltages (~2.5 V) and low switching voltages (1.5 V); good cycle-to-cycle and device-to-device uniformities, reasonable endurance ( 1E7 cycles) and retention property (> 4E4 s @125 °C). Furthermore, self-assembly patterned single-layer HfOx-based RRAM devices is demonstrated with faster switching speed (~50 ns), multi-level storage (2 bits/cell), longer endurance (> 1E9 cycles), half-selected read immunity (~1E9 cycles), good retention (> 1E5 s @ 125 °C) compared to bi-layer TiOx/HfOx device. Despite the recent advancement on the performance of RRAM devices, however, aiming at mass production, one of the most challenging tasks is to address the concern on the broad dispersion of switching parameters, i.e. cycle-to-cycle uniformity within one device and device-to-device uniformity, which are generally observed in the RRAM cells. HfOx/AlOx bi-layer RRAM devices show a better switching uniformity of the switching voltages and resistances than the single-layer HfOx devices. Despite the improvements on the uniformity, the forming process is still unavoidable. We also explore the use of TiOx/HfOx bi-layer device to achieve forming-free and better uniformity in switching parameters at the same time. Forming-free TiOx/HfOx devices are reported with good cycle-to-cycle uniformity in one device and device-to-device uniformity. Over 1E8 switching cycles is observed. TiOx can be used as an effective buffer layer to improve the uniformity in RRAM device. Finally, AlOx-based resistive switching device (RRAM) with multi-level storage capability was investigated for the potential to serve as an electronic synapse device. The Ti/AlOx/TiN memory stack with memory size 0.48 [micrometers×0.48 [micrometers] was fabricated; the resistive layer AlOx was deposited using ALD method. Multi-level resistance states were obtained by varying the compliance current levels or the applied voltage amplitudes during pulse cycling. These resistance states are thermally stable for over 1E5 s at 125 °C. The memory cell resistance can be continuously increased or decreased from each pulse cycle to pulse cycle. More than 1E5 endurance cycles and reading cycles were demonstrated. We further study the potential using this AlOx-based RRAM as electronic synapse device. Around 1% resistance change per pulse cycling was achieved and a plasticity learning rule pulse scheme was proposed to implement the memory device in large-scale hardware neuromorphic computing system.

Study On The Copper Based Resistive Random Access Memory Rram Devices

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Author :
language : en
Publisher:
Release Date : 2014

Study On The Copper Based Resistive Random Access Memory Rram Devices written by and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2014 with categories.

Resistive Switching Random Access Memory Rram

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Author : Zizhen Jiang
language : en
Publisher:
Release Date : 2020

Resistive Switching Random Access Memory Rram written by Zizhen Jiang and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2020 with categories.

In computing systems, memories are storage devices that keep instructions and data. To balance the performance and cost of modern computing systems, a hierarchy of memories--registers, caches, main memory, and storage--with different speeds and densities (costs) are utilized. In the memory hierarchy, a major performance gap between main memory and storage has become the bottleneck for many data-centric applications. Bridging this performance gap in the hierarchy has been the motivation of the development of many new memories. Among these new memories, resistive switching random access memory (RRAM) is a promising candidate for the next-generation non-volatile memory. Due to its simple structure, direct over-write, bit-alterability, fast speed, and low energy consumption, RRAM shows great potential for being used as both off-chip and on-chip binary digital memories. Additionally, the analog conductance modulation of RRAM allows it to be used as analog weights for machine learning specialized and neuromorphic computing hardware. This thesis presents the analysis, modeling, and characterization of RRAM that enable it to be used in both future digital memory systems and machine learning specialized/neuromorphic computing hardware. In Chapter 1, I review the development of memories in computing systems and the fundamentals of RRAM, followed by a discussion of the challenges for RRAM-based applications. Some of the key challenges include: 1) developing large-scale ultrahigh-density 3D VRRAM memory; 2) modeling of RRAM for circuit- and system-level design explorations; 3) achieving bidirectional analog conductance modulation of RRAM devices for using them as analog weights in the neural networks. These challenges are further discussed and addressed in Chapter 2 to 4 respectively. In Chapter 2, I investigate design guidelines from device to architecture levels to achieve ultrahigh-density 3D vertical resistive switching memory (VRSM). An accurate and computationally efficient simulation platform is developed to establish the write/read margins of 3D VRSM architectures. Using this simulation platform, I analyze the requirements of memory, selector, pillar driving transistors (pillar driver), array layout, and architecture floor plan. The analysis indicates: 1) small footprint pillar drivers are necessary for a high pillar areal density; 2) organizing the arrays into an architecture using the compact staircase and highly conductive wordplane connection (WPC) maximizes array efficiency and chip density; 3) the hexagon array with large low resistance state (LRS) and adequate nonlinearity (NL) is required for ultra-dense 3D VRSM. Compared to the most advanced 3D NAND, 3D VRSM has 46% higher chip density and shows better potential for future ultra-dense storage. In Chapter 3, I develop a dynamic Verilog-A RRAM compact model for circuit- and system-level design explorations. This model not only captures the DC and AC behaviors of RRAM devices, but also includes their intrinsic random fluctuations and variations. A methodology to systematically calibrate the model parameters with experimental data is presented and illustrated with a broad set of experimental data using multi-layer and doped RRAM devices. The physical meanings of these model parameters are also discussed. Lastly, I provide an example of applying the RRAM cell model to a TCAM macro. Tradeoffs on the design of RRAM devices for the TCAM macro are discussed in the context of the energy consumption and worst-case latency of the memory array. In Chapter 4, I examine the temperature-dependent characterization of RRAM devices using micro thermal stages (MTS) and provide a programming scheme (SRA: small RESET voltage amplitude and appropriate SET voltage) to achieve bidirectional analog conductance modulation of RRAM devices. I find that both abrupt and gradual SET can be obtained for the same device. The controlling parameters for modulating the gradual SET behavior are the SET voltage and the local device temperature. The results suggest that the filament morphology before SET is the key to understanding this phenomenon: gradual SET is obtained when the filament has a single-layer gap in the RESET state, and abrupt SET is obtained when the filament has a multi-layer gap in the RESET state. Additional temperature-dependent characterization is also applied to the RRAM during forming, read, write, and reliability measurements for both DC and AC conditions. Finally, I conclude the thesis with a summary of contributions and a brief outlook on future work of RRAM. Future work on one selector one RRAM (1S1R) cells and conductance modulation of RRAM devices can further facilitate the development of RRAM-based applications: 1) further investigation is needed to achieve 1S1R cells with large LRS and adequate NL; 2) modeling of bidirectional conductance modulation can be useful for the analysis of RRAM-based neural networks; 3) characterization of the conduction mechanisms and simulations on the conductance modulation during SET can be helpful in understanding the physics behind analog conductance modulation; 4) thermal engineering on the RRAM devices, such as capping layer and thermal insulation, can modulate the analog conductance modulation and improve the characteristics of RRAM for neural networks.

Interface Engineering In Binary Metal Oxide Based Resistive Random Access Memory Rram Devices

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Author : Sheng-Yu Wang
language : en
Publisher:
Release Date : 2011

Interface Engineering In Binary Metal Oxide Based Resistive Random Access Memory Rram Devices written by Sheng-Yu Wang and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2011 with categories.

Cerium Oxide Based Resistive Random Access Memory Devices

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Author : Cheng-Chih Hsieh
language : en
Publisher:
Release Date : 2017

Cerium Oxide Based Resistive Random Access Memory Devices written by Cheng-Chih Hsieh and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2017 with categories.

Resistive Random Access Memory (RRAM) is an emerging technology of non-volatile memory (NVM). Although the observation of metal oxide that can undergo an abrupt insulator-metal transition into a conductive state has been known for over 40 years, researchers started investigating those materials for memory applications in late 1990s. It has been considered as the next generation memory technology to replace current flash memory because RRAM has demonstrated feasible switching characteristics and potential to build high density arrays and also RRAM is also compatible with contemporary CMOS processes, which means RRAM can be integrated into current CMOS chips. While the structure of RRAM is a simple metal-insulator-metal (MIM) device, there are numerous materials that exhibit resistive switching. The switching behavior is not only dependent on the switching layer materials but also dependent on the choice of metal electrodes and their interfacial properties. Many metal oxides such as hafnium oxide, titanium oxide, aluminum oxide, nickel oxide (NiO), tantalum oxide and etc. have been studied in details; however, some materials are unexplored such as cerium oxide. In addition to nonvolatile storage applications, RRAM is considered as one of essential elements for advancing neuromorphic computing because of its analog switching and retention characteristics. This thesis investigated CeO[subscript x]-based RRAMs, from its fundamental device characteristics to neuromorphic applications.

Effect Of Thermal Treatment On Resistive Random Access Memory Rram Of Ni

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Author : 陳信宇
language : en
Publisher:
Release Date : 2009

Effect Of Thermal Treatment On Resistive Random Access Memory Rram Of Ni written by 陳信宇 and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2009 with categories.

Advances In Applied Materials And Electronics Engineering Ii

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Author : Brendan Gan
language : en
Publisher: Trans Tech Publications Ltd
Release Date : 2013-04-24

Advances In Applied Materials And Electronics Engineering Ii written by Brendan Gan and has been published by Trans Tech Publications Ltd this book supported file pdf, txt, epub, kindle and other format this book has been release on 2013-04-24 with Technology & Engineering categories.

Selected, peer reviewed papers from the 2013 2nd International Conference on Applied Materials and Electronics Engineering (AMEE 2013), April 19-20, 2013, Hong Kong

Selector Less Resistive Random Access Memory Rram With Intrinsic Nonlinearity For Crossbar Array Applications

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Author : Ying-Chen Chen
language : en
Publisher:
Release Date : 2019

Selector Less Resistive Random Access Memory Rram With Intrinsic Nonlinearity For Crossbar Array Applications written by Ying-Chen Chen and has been published by this book supported file pdf, txt, epub, kindle and other format this book has been release on 2019 with categories.

With increasing demand for high-density memory applications, alternative memory technology has been intensively investigated for replacing conventional charge-based flash memory. Among the emerging memory technology, resistive random-access memory (RRAM) device holds great potential as an emerging candidate because of its simple design, high-speed operation, excellent scalability and low power consumption. However, the sneak path current (I [subscript sneak]) through unselected neighboring cells is a major problem in crossbar RRAM array configuration, which significantly affects the read operation and accuracy. To address the sneak path current issue, a transistor or a selector device is typically integrated with the memory device i.e. 1T-1R and 1S-1R configurations. Unfortunately, integrating an additional selector device considerably increases the manufacturing complexity and cost. In this work, the selectorless 1R-only RRAM with self-rectifying behavior i.e. nonlinearity are proposed for suppressing the sneak path current without utilizing transistors or selector devices. Bilayer structures i.e. high-k layer/low-k layer stacks are highly scalable, while suppressing the sneak path currents in crossbar RRAM array. The nonlinearity (NL) modulation is also investigated by different operating schemes. The nonlinearity with calculated array size (N=120) utilizing the bilayer selectorless RRAM devices has been demonstrated. In addition, the nonlinearity can be modulated by utilizing various operation schemes, i.e. SET compliance current limit, positive pulse modulation, V-sweep, and I-sweep etc. The numerical read margin calculation of selectorless RRAM for crossbar array applications, device area effect, device thickness effect, and various operation schemes for good energy efficiency are also discussed. The result presents comprehensive insights into development and optimization of bilayer selectorless RRAMs with high nonlinearity (~120), good memory window (~102), and low switching energy (~40 pJ/bit), which enable the high- density storage, low-power crossbar array memory applications